Latch-up elimination in bulk CMOS LSI circuits
Conference
·
OSTI ID:5268731
Recent data on latch-up prevention in CMOS LSI circuits by the use of epitaxial starting material are presented, a modification of the lumped transistor SCR model is discussed, and a useful graphical solution to the latch-up problem is described.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- EY-76-C-04-0789
- OSTI ID:
- 5268731
- Report Number(s):
- SAND-80-0844C; CONF-800703-3
- Country of Publication:
- United States
- Language:
- English
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Cermets
& Refractories-- Radiation Effects
42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
ELECTRONIC CIRCUITS
FAILURES
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
PERFORMANCE TESTING
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
SEMICONDUCTOR DEVICES
TESTING
TRANSISTORS