Strategy for hierarchical error correction in smart memories

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:5369216

Murphy, S A

Yield, reliability, current, and power considerations impose severe constraints on the architecture of systems implemented with Water-Scale Integration (WSI). Not all systems are amenable to WSI, but some are and, where that is the case, benefits are overwhelming. Memories for raster-scan displays are excellent examples of integrable systems; they are highly regular, inherently fault-tolerant, and the duty cycle can be short. The feasibility question hinges on yield and reliability. To increase yield and reliability, hierarchical redundancy is used, static redundancy for yield and dynamic redundancy for reliability. In memories a few spare elements go far. In processors, however, expensive triple redundancy is best. Therefore, a WSI smart memory comprises a large memory with a small processor. The smart memory concept is adopted on an anti-Rent strategy. For efficiency in error correction, words are long --64 bits. The placement of bits in the memory is dictated by alpha-particle considerations; a single alpha-particle should precipitate no more than one error per word. Both lasers and EPROMs are used for repair; lasers eliminate blocks that have shorting faults, EPROM's fix logic faults. This thesis presents the architecture and selected circuit details of a 64-bit processor and 512K-bytes of static RAM.

• Research Organization: Minnesota Univ., Minneapolis (USA)
• OSTI ID: 5369216
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTER ARCHITECTURE
COMPUTERS
CORRECTIONS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
ERRORS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
RELIABILITY