Superconducting single flux quantum 20 Gb/s clock recovery circuit

Journal Article · Tue Jul 01 04:00:00 EDT 1997 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.119449· OSTI ID:531710

Kaplunenko, V; Borzenets, V; Dubash, N ^[1]; Van Duzer, T ^[2]

---

1. Conductus, 969 West Sunnyvale, California 94086 (United States)
2. University of California, Berkeley, California 94720 (United States)

A clock recovery circuit has been successfully tested at frequencies up to 20 GHz. This cell is designed for a rapid-single-flux-quantum (RSFQ) telecommunication data switch. It serves to set the receiver clock in phase with the incoming digital signal. The circuit consists of a dc-to-SFQ converter, ring oscillator [(RO) is a closed-loop RSFQ Josephson transmission line], confluence buffer, and an 8-bit binary counter. The input signal transforms to SFQ pulses, and each pulse resets the phase of the ring oscillator, giving a locking time of 1 bit. Thus, the pull-in (capture) range and hold-in (tracking) range are the same, and strictly depend on the encoding of the input signal. This range is estimated to be about 1 GHz at frequency 20 GHz, if the sequence of consecutive ONEs or ZEROs does not exceed 20 bits. The quality factor Q{sub RO} of ring oscillator is about 2000, which gives a jitter of 50 fs for a 35-junction RO. A sampling technique was used to demonstrate phase recovery (phase locking) with only one incoming pulse per 512 clock periods. {copyright} {ital 1997 American Institute of Physics.}

• OSTI ID: 531710
• Journal Information: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 1 Vol. 71; ISSN APPLAB; ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

66 PHYSICS
COMMUNICATIONS
DESIGN
DIGITAL SYSTEMS
INTEGRATED CIRCUITS
SUPERCONDUCTING DEVICES
SWITCHES
TIMING CIRCUITS