Scaling of Josephson logic circuits
The effects of scaling on digital Josephson circuits is investigated. The dependence of gate delay on junction and circuit parameters are estimated using both analytic approximations and circuit simulations with the resistively shunt junction (RSJ) model. Comparisons of the simulations based on the RSJ model and the microscopic model show that for digital circuits the RSJ model is a good approximation. It was found that, at the gate level, Josephson logic gates can be scaled in such a way that the speed of the gate is independent of junction size for junction dimensions less than a Josephson penetration depth, which is about 4 {mu}m or greater for Nb and Pb-alloy junctions. To measure gate delays, a process for fabricating high-quality, high-current-density junctions with uniform critical currents has been developed. This process also pushed the minimum junction dimension down to 1 {mu}m from the 5 {mu}m minimum of the existing process. For large-scale Josephson integrated circuits, the model suggests that due to power and circuit-density considerations, a junction size of {le}1 {mu}m is needed to obtain optimal performance for Nb and Pb-alloy junction technology.
- Research Organization:
- California Univ., Berkeley, CA (USA)
- OSTI ID:
- 5237398
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
ANALYTICAL SOLUTION
ELECTRONIC CIRCUITS
GATING CIRCUITS
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
PENETRATION DEPTH
SCALING LAWS
SIMULATION
SUPERCONDUCTING JUNCTIONS