A multiprocessor data flow accelerator module
Conference
·
OSTI ID:5180827
Real-time controllers often need to minimize the latency between the arrival of a stimulus and the delivery of a control signal. Using multiprocessors to compute the control algorithm is appealing for these applications, but problem decomposition and load leveling are not straightforward. The data flow model of computation offers a solution which can be implemented for shared memory, parallel processors by the addition of a single circuit board. A typical parallel processor, the data flow model, and several versions of the Data flow Accelerator Module (DFAM) are presented together with some preliminary results. 15 refs., 12 figs.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 5180827
- Report Number(s):
- SAND-88-0622C; CONF-880577-2; ON: DE88007587
- Country of Publication:
- United States
- Language:
- English
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