HPSm: Exploiting concurrency to achieve high performance in a single-chip microarchitecture

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:5145687

Hwu, W W

This dissertation demonstrates that substantial speedup over conventional single-chip microarchitectures can be achieved by a single-chip microarchitecture exploiting deep pipelining, out-of-order execution, multiple operations per instruction, and multiple function units. The authors characterizes the behavior of program parallelism available in several real-world workloads. The parallelism is sufficiently localized that a microarchitecture exploiting parallelism among a small number of instructions at a time can achieve most of the speedup available. One of the most difficult problems in the design of a concurrent microarchitecture is exception handling. A checkpoint repair mechanism here demonstrates that a microarchitecture exploiting local parallelism need not suffer from inconsistent states when exceptions occur. HPSm, a single-chip microarchitecture, was designed as the first prototype of the execution model exploiting local parallelism. Concise descriptions of the critical components are given, and how they interact illustrated.

• Research Organization: California Univ., Berkeley, CA (USA)
• OSTI ID: 5145687
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTER ARCHITECTURE
COMPUTERS
COST
DESIGN
ELECTRONIC CIRCUITS
EVALUATION
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
PARALLEL PROCESSING
PROGRAMMING
VECTOR PROCESSING