Exploiting fine grain parallelism in Prolog

Book · Mon Jan 01 04:00:00 EST 1990

OSTI ID:5361435

Singhal, A

The goals of this paper is to design a Prolog system that automatically exploits parallelism in Prolog with low overhead memory management and task management schemes, and to demonstrate by means of detailed simulations that such a Prolog system can indeed achieve a significant speedup over the fastest sequential Prolog systems. The authors achieve these goals by first identifying the large sources of overhead in parallel Prolog execution: side-effects caused by parallel tasks, choicepoints created by parallel tasks, tasks creation, task scheduling, task suspension and context switching. The authors then identify a form of parallelism, called flow parallelism, that can be exploited with low overhead because parallel execution is restricted to goals that do not cause side-effects and do not create choicepoints. The authors develop a master-slave model of parallel execution that eliminates task suspension and context switching. The model uses program partitioning and task scheduling techniques that do not require task suspension and context switching to prevent deadlock. The authors identify architectural techniques to support the parallel execution model and develop the Flow Parallel Prolog Machines (FPPM) architecture and implementation. Finally, the authors evaluate the performance of FPPM and investigate the design tradeoffs using measurements on a detailed, register- transfer level simulator. FPPM achieves an average speedup of about a factor of 2 (as much as a factor of 5 for some programs) over the current highest performance sequential Prolog implementation, the VLSI-BAM. The speedups over other parallel Prolog systems are much larger.

• OSTI ID: 5361435
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTER ARCHITECTURE
DESIGN
MEMORY MANAGEMENT
PARALLEL PROCESSING
PROGRAMMING
PROGRAMMING LANGUAGES
PROLOG
SIMULATION