Parallel processing and VLSI architectures for syntactic pattern recognition and image analysis
Computation speed of syntatic pattern recognition and image analysis algorithms have always been regarded as slow. Several parallel processing techniques are proposed, especially for the syntatic analyzer, to speed up the computation. The distance calculations between strings and trees have been implemented on three different parallel processing systems, namely, the SIMD system, the dedicated SIMD system and the MIMD system. The results show that distance calculation can be sped up when it is implemented on a parallel computer. Earley's algorithm has wide applications in many fields. A parallel Earley's algorithm is proposed, and the recognition algorithm is implemented on a VLSI architecture, the parse extraction algorithm and the complete algorithm on a processor array. This parallel execution only takes linear time. Simulation results prove the correctness of this design. The same Earley's algorithm has been extended to process erroneous input data. This error-correcting syntatic recognizer has also been implemented on a VLSI system. The results from the simulation not only prove the correctness of this design, but also indicate that this recognizer can be used to classify patterns.
- OSTI ID:
- 5116089
- Country of Publication:
- United States
- Language:
- English
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