Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Parallelizing the SDI ACCESS algorithm for the Connection Machine-2

Technical Report ·
DOI:https://doi.org/10.2172/5087840· OSTI ID:5087840

Argonne National Laboratory (ANL) has developed considerable expertise in developing and optimizing algorithms on a collection of multiprocessor computers. One aspect of Argonne research in parallel computing, funded in part by the Command Center/System Operation and Integration Functions Program of the Strategic Defense Initiative Organization, involves the speed and other properties of parallel SDI algorithms. Various algorithms under study have exhibited speedups resulting from parallelization on shared-memory machines. A weapon-target accessibility algorithm called ACCESS exhibited a high degree of inherent parallelism and has been studied on a wide variety of sequential and parallel multiple instruction multiple data machines. To study ACCESS on a massively parallel single instruction multiple data (SIMD) machine architecture, ANL researchers developed a version of ACCESS on a Thinking Machines Corporation 16K processor Connection Machine-2 (CM-2) located at the ACRF. ANL researchers wrote the Connection Machine version of ACCESS in C, a version of C by Thinking Machines Corporation with extensions to accommodate SIMD parallelism. Because of the large number of available physical processors and the ability to create virtual processors on the CM-2, the Connection Machine version of ACCESS was able to process an array of 128 {times} 1024 tasks in parallel. The CM-2 implementation of ACCESS was faster than both the parallel version run on the Alliant FX/8, the Encore Multimax, and the Sequent Balance and the sequential version run on the ANL Cray X-MP/14. For the benchmark ACCESS problem, the CM-2 at ANL with 16K processors achieved a sustained performance of 400 Mflops. The investigation has demonstrated that achieving optimal performance requires structuring the code carefully to keep all available processors busy and to reduce disruptive communication on the front-end processor. 4 refs., 5 figs., 6 tabs.

Research Organization:
Argonne National Lab., IL (USA)
Sponsoring Organization:
DOE/ER
DOE Contract Number:
W-31109-ENG-38
OSTI ID:
5087840
Report Number(s):
ANL-89/41; ON: DE90006382
Country of Publication:
United States
Language:
English