New bus architecture for distributed avionic systems
Conference
·
OSTI ID:5081426
The authors discuss a bus architecture which offers several advantages over conventional buses for a large selection of applications, and which allows for both interrupts and error checking. The bus may be expanded in the form of a tree with many processors, memories, and input/output devices distributed freely throughout the system. Therefore, it is inherently a multiprocessor bus and is well suited for systems in which a central controller controls several subordinate processors and devices. Its low overhead plus large capacity for expansion make it appropriate for a wide range of future systems.
- OSTI ID:
- 5081426
- Resource Relation:
- Conference: Sponsored by IEEE, Seattle, WA, USA, 31 Oct 1983
- Country of Publication:
- United States
- Language:
- English
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