Hardware considerations in the implementation of a segment display processor architecture
Conference
·
OSTI ID:5070710
The segment display processor (SDP) provides a general architecture for the processing and merging of multiple format graphics or image data on a raster scan output medium such as a CRT or laser scanner. The work addresses some of the issues relating to the development of a high performance implementation of the SDP as a hierarchical multiprocessor. Among the major considerations that are dealt with are representation of control and image data structures, interprocesor communications and bus structures, use of parallel and pipeline processor organization, and the design approach used for the logical interface to the host system. 14 references.
- OSTI ID:
- 5070710
- Country of Publication:
- United States
- Language:
- English
Similar Records
Parallel architectures for computer graphics displays
Pipeline architecture for image segmentation
Architecture for the real-time display and manipulation of three-dimensional objects
Thesis/Dissertation
·
Mon Dec 31 23:00:00 EST 1984
·
OSTI ID:5673317
Pipeline architecture for image segmentation
Conference
·
Thu Dec 31 23:00:00 EST 1981
·
OSTI ID:5179064
Architecture for the real-time display and manipulation of three-dimensional objects
Conference
·
Fri Dec 31 23:00:00 EST 1982
·
OSTI ID:5364545