Parallel architectures for computer graphics displays

Thesis/Dissertation · Tue Jan 01 04:00:00 EST 1985

OSTI ID:5673317

Hannah, M R

This thesis investigates the use of VLSI-based parallel architectures in two aspects of computer graphics display hardware. First, a flexible multiprocessor pipeline architecture for geometric computation is described. Second, the architecture and algorithms of a distributed processing array for smooth-shaded scan conversion of three-dimensional geometric image descriptions is presented. Frame buffers driving raster-scanned displays have recently become the technology of choice for computer graphics because of their flexibility and relatively low cost. Two graphics methodologies have evolved for programming these displays - bit-map and geometric. Geometric graphics, although more convenient from the user's standpoint, has previously required expensive hardware support to avoid slow system response. The Geometry Engine (Clark 82) is a low cost, VLSI-based architecture for providing the hardware support necessary for interactive geometric graphics. This work extends the Geometry Engine architecture to support smooth shaded rendering, and higher performance systems. A multi-processor raster subsystem is described that is easily scaled from few to many processors, while simultaneously solving the problems of memory bandwidth and computational throughput.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 5673317
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARCHITECTURE
ARRAY PROCESSORS
COMPUTER GRAPHICS
DATA PROCESSING
DISPLAY DEVICES
DISTRIBUTED DATA PROCESSING
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PROCESSING
PROGRAMMING