A prototype functional language implementation for hierarchical-memory architectures
The first implementation of Sisal was designed for general shared-memory architectures. Since then, we have optimized the system for vector and coherent-cache multiprocessors. Coherent-cache systems can be thought of as simple, two-level hierarchical memory systems, where the memory hierarchy is managed by the hardware. The compiler and run-time system for such an architecture needs to maintain data locality so that the processor caches are used as much as possible. In this paper, we extend the coherent-cache implementation to include explicit compiler and run-time control for medium-grain and coarse-grain hierarchical-memory architectures. We implemented the extended system on the BBN Butterfly using interleaved shared memory exclusively for the purposes of data sharing and exploiting the per-processor local memories. We give preliminary performance results for this extended system. 10 refs., 7 figs.
- Research Organization:
- Lawrence Livermore National Lab., CA (United States)
- Sponsoring Organization:
- DOE; USDOE, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 5001169
- Report Number(s):
- UCRL-JC-107437; CONF-920114--1; ON: DE91015140
- Country of Publication:
- United States
- Language:
- English
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