Enhanced superscalar hardware: The schedule table

Conference · Fri Dec 31 04:00:00 EST 1993

OSTI ID:46259

Pickett, J K; Meyer, D G ^[1]

---

1. Purdue Univ., Lafayette, IN (United States)

In the push for ever increasing performance out of processor architectures, there is a need to expand beyond the limitations of existing scalar approaches. Superscalar architectures provide one such means. By dynamically executing more than one instruction per clock cycle, superscalar architectures can improve performance without relying solely on technology improvements for these gains. This paper examines a new technique for superscalar control implementation, called the schedule table. The schedule table facilitates dependency checking, out of order instruction issue, out of order execution, branch prediction, speculative execution, precise interrupts, and fast and efficient misprediction recovery.

• OSTI ID: 46259
• Report Number(s): CONF-931115--
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
COMPUTER ARCHITECTURE
DESIGN
MEMORY DEVICES
MICROPROCESSORS
PARALLEL PROCESSING
PERFORMANCE