Profile-assisted instruction scheduling

Journal Article · Fri Apr 01 04:00:00 EST 1994 · International Journal of Parallel Programming

DOI:https://doi.org/10.1007/BF02577873· OSTI ID:379410

Chen, W Y; Mahlke, S A; Warter, N J; Anik, S; Hwu, Wen-Mei W ^[1]

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1. Univ. of Illinois, Urbana, IL (United States)

Instruction schedulers for superscalar and VLIW processors must expose sufficient instruction-level parallelism to the hardware in order to achieve high performance. Traditional compiler instructure scheduling techniques typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase instruction-level parallelism for the frequent execution scenarios at the expense of the less frequent ones. Profile information identifies these important execution scenarios in a program. In this paper, two major categories of profile information are studied: control-flow and memory-dependence. Profile-assisted code scheduling techniques have been incorporated into the IMPACT-I compiler. These techniques are acyclic global scheduling and software pipelining. This paper describes the scheduling algorithms, highlights the modifications required to use profile information, and explains the hardware and compiler support for dealing with hazards that arise from aggressive use of profile information. The effectiveness of these profile-based scheduling techniques is evaluated for a range of super-scalar and VLIW processors.

• Sponsoring Organization: USDOE
• OSTI ID: 379410
• Journal Information: International Journal of Parallel Programming, Journal Name: International Journal of Parallel Programming Journal Issue: 2 Vol. 22; ISSN IJPPE5; ISSN 0885-7458
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
ARRAY PROCESSORS
PARALLEL PROCESSING
TASK SCHEDULING
TRANSLATORS