Micro benchmark analysis of the KSR1
- Univ. of Southern California, Los Angeles, CA (United States). Computer Science Dept.
- USC/Information Sciences Inst., Marina del Rey, CA (United States)
A new approach, micro benchmarks, has recently been developed. Using this technique, the authors have analyzed the KSR1, and in particular the ``ALLCACHE`` memory architecture and ring interconnection. They have been able to elucidate many facets of memory performance. The technique has enabled them to identify and characterize parts of the memory design not described by Kendall Square Research. Their results show that a miss in the local cache can incur a penalty ranging from 7.5 microseconds to 500 microseconds (when a dirty ``page`` in the local cache must be evicted). The programmer must be very careful in placement and accessing of data to obtain maximum performance from the KSR1; the data presented here will help in understanding the performance actually obtained.
- OSTI ID:
- 46218
- Report Number(s):
- CONF-931115--
- Country of Publication:
- United States
- Language:
- English
Similar Records
The KSR1: Experimentation and modeling of poststore
The KSR1: Experimentation and modeling of poststore