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SEGR and SEB in n-channel power MOSFETs

Journal Article · · IEEE Transactions on Nuclear Science
DOI:https://doi.org/10.1109/23.556887· OSTI ID:445460
; ; ; ;  [1]; ; ;  [2];  [3];  [4]
  1. Univ. of Arizona, Tucson, AZ (United States). Electrical and Computer Engineering Dept.
  2. Univ. Montpellier II (France). Centre d`Electronique de Montpellier
  3. Naval Surface Warfare Center, Crane, IN (United States)
  4. Wheatley (C.F.), Drums, PA (United States)

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.

Sponsoring Organization:
Defense Nuclear Agency, Washington, DC (United States); National Aeronautics and Space Administration, Washington, DC (United States)
OSTI ID:
445460
Report Number(s):
CONF-960773--
Journal Information:
IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 43; ISSN 0018-9499; ISSN IETNAE
Country of Publication:
United States
Language:
English

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