D0 muon readout electronics design
- Fermilab
- Serpukhov, IHEP
The readout electronics designed for the DO Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the DO Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16-bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed
- Research Organization:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 434911
- Report Number(s):
- FERMILAB-CONF-96-404; oai:inspirehep.net:428455
- Journal Information:
- IEEE Trans.Nucl.Sci., Journal Name: IEEE Trans.Nucl.Sci. Vol. 44
- Country of Publication:
- United States
- Language:
- English
D0 upgrade muon electronics design
|
journal | August 1995 |
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