CMOS optimization for radiation hardness
Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO$sub 2$ gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al$sub 2$$O$$sub 3$ as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation- hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented. (WHK)
- Research Organization:
- Sandia Labs., Albuquerque, N.Mex. (USA)
- NSA Number:
- NSA-33-005641
- OSTI ID:
- 4184779
- Report Number(s):
- SAND--75-5731; CONF-751206--1
- Country of Publication:
- United States
- Language:
- English
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