Linear Fresnel zone plate based two-state alignment system for 0.25 micron x-ray lithography
X-ray lithography has proven to be a cost effective and promising technique for fabricating Integrated Circuits (ICs) with minimum feature sizes of less than 0.25 {mu}m. Since IC fabrication is a multilevel process, to preserve the functionality of devices, circuit patterns printed at each lithography level must match existing patterns on the wafer with an accuracy of less than 1/3 {approximately} 1/5 of the minimum feature size. An alignment system is used to position the mask relative to the wafer so that mask circuit patterns can be printed on the wafer at the designed position. As the minimum printed feature size shrinks, the overlay requirements of a lithography tool become more stringent. A stepper for 0.25 {mu}m feature device fabrication requires an overlay accuracy of 0.075 {mu}m, of which only 0.05 {mu}m (mean + 3{sigma}) is allocated to its alignment system. This thesis presents the development of a linear Fresnel zone late based two-state alignment (TSA) method for a 0.25 {mu}m x-ray lithography tool. The authors first analyze the overlay requirement in a lithography process and the error allocation to the alignment system for a 0.25 {mu} feature x-ray lithography tool. They then describe the principle of the two-state alignment, its computer simulation and the optimal alignment mark design. They carried out an optical bench test for the one-axes alignment setup and experimentally evaluated the performance of the system. They developed a three-axes TSA system and integrated the system with the ES-3 x-ray beamline to construct the CXrL aligner, an experimental x-ray exposure system in CXrL. They measured the alignment accuracy of the exposure system to be better than 0.035 {mu}m (3{sigma}) on both metal and dielectric alignment mark substrates. They also studied the effect of processing coatings on the alignment signal with different wafer mark substrates. They successfully printed the 0.5 {mu}m gate level patterns for the first NMOS test chip at CXrL.
- Research Organization:
- Wisconsin Univ., Madison, WI (United States)
- OSTI ID:
- 39362
- Country of Publication:
- United States
- Language:
- English
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