Improved Si{sub 3}N{sub 4}/Si/GaAs metal-insulator-semiconductor interfaces by {ital in} {ital situ} anneal of the as-deposited Si
- Coordinated Science Laboratory and Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 South Goodwin Avenue, Urbana, Illinois 61801 (United States)
Si interlayers in GaAs metal-insulator-semiconductor structures are essential for interfaces with device quality. The incompatible growth temperature of Si on GaAs, however, presents a dilemma between the crystallinity of Si and the stoichiometry of GaAs. We circumvented this dilemma by a new approach: a high-temperature {ital in} {ital situ} anneal following the low-temperature Si deposition. The idea is that the GaAs surface covered with a few monolayers of Si can stand a much higher temperature, and the crystal quality of the Si is resumed during the high-temperature anneal. The surface morphology of the as-deposited and the {ital in} {ital situ} annealed Si was examined with a scanning tunneling microscope, the results of which confirmed high crystal quality of the Si layer and full coverage of the GaAs surface. With {ital in} {ital situ} anneal, interface trap densities of high 10{sup 10} eV{sup {minus}1} cm{sup {minus}2} were routinely obtained in Si{sub 3}N{sub 4}/Si/GaAs metal-insulator-semiconductor capacitors, as determined with conductance measurements.
- Research Organization:
- University of Illinois
- DOE Contract Number:
- FG02-91ER45439
- OSTI ID:
- 29258
- Journal Information:
- Journal of Applied Physics, Journal Name: Journal of Applied Physics Journal Issue: 8 Vol. 77; ISSN JAPIAU; ISSN 0021-8979
- Country of Publication:
- United States
- Language:
- English
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