Practical applications of backside silicon etching
- Texas Instruments, Houston, TX (United States)
As the complexity of the integrated circuits increases, deprocessing becomes a challenging job due to multilevel metallization and planarization processes. Deprocessing issues associated with failure analysis of the trench capacitors in DRAM devices are well known and various techniques to inspect the trenches from the backside have been widely published. These backside etching techniques can also be applied to failure analysis of other multilayer metallization devices for efficient inspection of gate oxide and contacts. This paper compares backside silicon etch (BSE) techniques using several etchants as well as various sample preparation methods. Practical applications of backside silicon etching of different devices have been described for DRAM and SRAM single cell failures and silicide contact failures where deprocessing from the top side is difficult. These examples show how BSE can be a very useful technique to characterize defects in a wide variety of devices.
- OSTI ID:
- 260541
- Report Number(s):
- CONF-951156--; ISBN 0-87170-554-0
- Country of Publication:
- United States
- Language:
- English
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