Schematic synthesis for die navigation during failure analysis
- Motorola Inc., Austin, TX (United States)
The increased complexity of microprocessors mandates the need for computer assisted navigation during failure analysis. In an ideal navigation environment, the device schematics and layout, and a motorized mechanical or electron beam probe station, are linked to provide an efficient analytical tool. Realization of a navigation system for a design requires the porting of the schematic and layout data from the design capture system to the navigation system. For a single design, an ad hoc conversion approach is practical. However, supporting the failure analysis of designs from multiple design organizations, each with its own specific design flow and tool set, necessitates a more generalized conversion methodology. This generalized methodology allows generation of schematics for those designs without them. The methodology uses off-the-shelf VLSI design tools as well as algorithms that are described.
- OSTI ID:
- 260534
- Report Number(s):
- CONF-951156--; ISBN 0-87170-554-0
- Country of Publication:
- United States
- Language:
- English
Similar Records
ISITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
ULYSSES - an expert-system-based VLSI design environment