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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Journal Article · · Cryptography
 [1];  [1];  [2];  [3]
  1. Univ. of New Mexico, Albuquerque, NM (United States)
  2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
  3. US Dept. of Defense, Fort Meade, MD (United States
+ Show Author Affiliations

Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (μP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the μP. In this paper, we propose a fault detection method that utilizes an ’engineered’ executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP.

Research Organization:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA); USDOD
Grant/Contract Number:
NA0003525
OSTI ID:
2341388
Report Number(s):
SAND--2024-05026J
Journal Information:
Cryptography, Journal Name: Cryptography Journal Issue: 2 Vol. 8; ISSN 2410-387X
Publisher:
MDPICopyright Statement
Country of Publication:
United States
Language:
English

References (13)

Error detection by duplicated instructions in super-scalar processors journal March 2002
Architectures for online error detection and recovery in multicore processors conference March 2011
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework conference October 2008
Design and Implementation of BIST conference December 2018
Fault: Open-Source EDA’s Missing DFT Toolchain journal April 2021
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation conference January 2007
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor journal March 2022
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults journal January 2024
Understanding the propagation of hard errors to software and implications for resilient system design journal March 2008
Automatic detection of fault attack and countermeasures conference October 2009
Fame conference June 2016
Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor journal August 2022
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case journal November 2022

Figures / Tables (13)

Figure 1(p. 4)figure Figure 1
Figure 2(p. 5)figure Figure 2
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Figure 4(p. 6)figure Figure 4
Figure 5(p. 7)figure Figure 5
Table 1(p. 8)table Table 1
Figure 6(p. 9)figure Figure 6
Table 2(p. 9)table Table 2
Figure 7(p. 10)figure Figure 7
Figure 8(p. 11)figure Figure 8
Figure 9(p. 12)figure Figure 9
Figure 10(p. 13)figure Figure 10
Table 3(p. 14)table Table 3

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Related Subjects

42 ENGINEERING
ATPG
DFT
FPGA
RISC-V
cryptography
fault analysis
fault detection
fault emulation
information leakage