Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

Journal Article · Sun Dec 07 04:00:00 EST 2014 · Journal of Applied Physics

DOI:https://doi.org/10.1063/1.4903520· OSTI ID:22402742

Lind, E.; Wernersson, L. E. ^[1]

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1. Department of Electrical and Information Technology, Lund University, Lund SE-221 00 (Sweden)

A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

• OSTI ID: 22402742
• Journal Information: Journal of Applied Physics, Journal Name: Journal of Applied Physics Journal Issue: 21 Vol. 116; ISSN JAPIAU; ISSN 0021-8979
• Country of Publication: United States
• Language: English

Related Subjects

71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
CAPACITANCE
CAPACITORS
DIELECTRIC MATERIALS
ELECTRONS
EQUIVALENT CIRCUITS
INDIUM ARSENIDES
INTERFACES
METALS
OXIDES
SEMICONDUCTOR MATERIALS
SIMULATION
THICKNESS
TRAPS