Current induced annealing and electrical characterization of single layer graphene grown by chemical vapor deposition for future interconnects in VLSI circuits

Journal Article · Mon Sep 15 04:00:00 EDT 2014 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.4895802· OSTI ID:22303539

Prasad, Neetu; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C. ^[1]; Bhatia, C. S. ^[2]

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1. Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110021 (India)
2. Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore)

Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ∼1.2 × 10{sup 7 }A/cm{sup 2} has been obtained for SLG (1 × 2.5 μm{sup 2}) on SiO{sub 2}/Si substrate, which is about an order higher than that of conventionally used copper interconnects.

• OSTI ID: 22303539
• Journal Information: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 11 Vol. 105; ISSN APPLAB; ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

75 CONDENSED MATTER PHYSICS
SUPERCONDUCTIVITY AND SUPERFLUIDITY
ANNEALING
CHEMICAL VAPOR DEPOSITION
COPPER
CURRENT DENSITY
CURRENTS
GRAIN BOUNDARIES
GRAPHENE
INTEGRATED CIRCUITS
POLYCRYSTALS
SILICON OXIDES
SUBSTRATES
SURFACES
TRAPPING