Low bias stress and reduced operating voltage in SnCl{sub 2}Pc based n-type organic field-effect transistors
- Department of Physics, Indian Institute of Technology Guwahati, Guwahati, Assam 781039 (India)
- (India)
Vacuum deposited tin (IV) phthalocyanine dichloride (SnCl{sub 2}Pc) field-effect transistors were fabricated on polymethylmethacrylate/aluminum oxide (PMMA/Al{sub 2}O{sub 3}) bilayer gate dielectric, with reduced operating voltage and low contact resistance. The devices with top contact Ag electrodes exhibit excellent n-channel behavior with electron mobility values of 0.01 cm{sup 2}/Vs, low threshold voltages ∼4 V, current on/off ratio ∼10{sup 4} with an operating voltage of 10 V. Bias stress instability effects are investigated during long term operation using thin film devices under vacuum. We find that the amount of bias stress of SnCl{sub 2}Pc based thin film transistor is extremely small with characteristic relaxation time >10{sup 5} s obtained using stretched exponential model. Stressing the SnCl{sub 2}Pc devices by applying 10 V to the gate for half an hour results in a decrease of the source drain current, I{sub DS} of only ∼10% under low vacuum. These devices show highly stable electrical behavior under multiple scans and low threshold voltage instability under electrical dc bias stress (V{sub DS} = V{sub GS} = 10 V, for 2 h) even after 40 days.
- OSTI ID:
- 22300153
- Journal Information:
- Applied Physics Letters, Vol. 104, Issue 21; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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