Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal–oxide–semiconductor/magnetic tunnel junction hybrid latches
- Center for Spintronics Integrated Systems, Tohoku University, Sendai 980-8579 (Japan)
The robustness of data load of metal–oxide–semiconductor/magnetic tunnel junction (MOS/MTJ) hybrid latches at power-on is examined by using Monte Carlo simulation with the variations in magnetoresistances for MTJs and in threshold voltages for MOSFETs involved in 90 nm technology node. Three differential pair type spin-transfer-torque-magnetic random access memory cells (4T2MTJ, 6T2MTJ, and 8T2MTJ) are compared for their successful data load at power-on. It is found that the 4T2MTJ cell has the largest pass area in the shmoo plot in TMR ratio (tunnel magnetoresistance ratio) and V{sub dd} in which a whole 256 kb cell array can be powered-on successfully. The minimum TMR ratio for the 4T2MTJ in 0.9 V < V{sub dd} < 1.9 V is 140%, while the 6T2MTJ and the 8T2MTJ cells require TMR ratio larger than 170%.
- OSTI ID:
- 22273778
- Journal Information:
- Journal of Applied Physics, Vol. 115, Issue 17; Conference: 55. annual conference on magnetism and magnetic materials, Atlanta, GA (United States), 14-18 Nov 2010; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0021-8979
- Country of Publication:
- United States
- Language:
- English
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