Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming
- Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States)
To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.
- OSTI ID:
- 22053543
- Journal Information:
- Journal of Vacuum Science and Technology. A, International Journal Devoted to Vacuum, Surfaces, and Films, Vol. 27, Issue 6; Other Information: (c) 2009 American Vacuum Society; Country of input: International Atomic Energy Agency (IAEA); ISSN 1553-1813
- Country of Publication:
- United States
- Language:
- English
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