A multi-channel time-to-digital converter chip for drift chamber readout

Conference · Fri Dec 01 04:00:00 EST 1995

OSTI ID:204677

Santos, D M ^[1]; Chau, A; DeBusshere, D; Dow, S; Flasck, J; Levi, M; Kirsten, F; Su, E ^[2]

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1. Aveiro Univ., Aveiro (Portugal)
2. Lawrence Berkeley Lab., CA (United States)

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8{mu} triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz.

• Research Organization: Lawrence Berkeley Lab., CA (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States)
• DOE Contract Number: AC03-76SF00098
• OSTI ID: 204677
• Report Number(s): LBL--38039; CONF-951073--22; ON: DE96005886
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
DATA PROCESSING
DESIGN
DIGITIZERS
DRIFT CHAMBERS
INTEGRATED CIRCUITS
READOUT SYSTEMS
TIME-TO-AMPLITUDE CONVERTERS