Single-even gate-rupture in power MOSFETs: Prediction of breakdown biases and evaluation of oxide thickness dependence

Journal Article · Thu Nov 30 23:00:00 EST 1995 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.489234· OSTI ID:203715

Allenspach, M; Brews, J R; Schrimpf, R D; Galloway, K F ^[1]; Mouret, I ^[1]; Titus, J L ^[2]; Pease, R L ^[3]; Wheatley, Jr, C F

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1. Univ. of Arizona, Tucson, AZ (United States)
2. Naval Surface Warfare Center, Crane, IN (United States)
3. RLP Research, Inc., Albuquerque, NM (United States)

Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for V{sub DS} = 0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.

• OSTI ID: 203715
• Report Number(s): CONF-950716--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 42; ISSN IETNAE; ISSN 0018-9499
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
CALCULATION METHODS
COMPARATIVE EVALUATIONS
HEAVY IONS
MOSFET
PHYSICAL RADIATION EFFECTS
PROBABILISTIC ESTIMATION