Worst case total dose radiation response of 0.35 {micro}m SOI CMOSFETs
Through experimental results and analysis by TSUPREM4/MEDICI simulations, the worst case back gate total dose bias condition is established for body tied SOI NMOSFETs. Utilizing the worst-case bias condition, a recently proposed model that describes the back n-channel threshold voltage shift as a function of total dose, TSUPREM4/MEDICI simulations, and circuit level SPICE simulations, a methodology to model post-rad standby current is developed and presented. This methodology requires the extraction of fundamental starting material/material preparation constants, and then can be utilized to examine post-rad stand-by current at the device and circuit level as function of total dose. Good agreement between experimental results and simulations is demonstrated.
- Research Organization:
- Honeywell Solid State Electronics Center, Plymouth, MN (US)
- OSTI ID:
- 20014746
- Journal Information:
- IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers) Journal Issue: 6Pt1 Vol. 46; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
Similar Records
Total dose radiation hard 0.35 {micro}m SOI CMOS technology
New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation