Plasma-based method for delayering of circuits

Shul, Randy J.; Friedman, Caitlin Rochford; Salazar, Gregory Paul; Rye, Michael J.; Sniegowski, Jeffry Joseph; Greth, Karl Douglas

Plasma-based method for delayering of circuits

Patent · Tue May 30 00:00:00 EDT 2023

OSTI ID:1998425

Shul, Randy J.; Friedman, Caitlin Rochford; Salazar, Gregory Paul; Rye, Michael J.; Sniegowski, Jeffry Joseph; Greth, Karl Douglas

The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.

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Research Organization:: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

Sponsoring Organization:: USDOE National Nuclear Security Administration (NNSA)

DOE Contract Number:: NA0003525

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Number(s):: 11,664,238

Application Number:: 16/941,676

OSTI ID:: 1998425

Country of Publication:: United States

Language:: English

References (16)

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