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Device and method for data compression using a metadata cache

Patent ·
OSTI ID:1987223
; ;
A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
11,604,738
Application Number:
16/146,543
OSTI ID:
1987223
Country of Publication:
United States
Language:
English

References (4)

Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads conference September 2012
An Introduction to Arithmetic Coding journal March 1984
G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs conference February 2017
Sc2 journal June 2014

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