Device and method for cache utilization aware data compression

Patent · Tue Nov 17 00:00:00 EST 2020

OSTI ID:1771643

Das, Shomit N.; Punniyamurthy, Kishore; Tomei, Matthew; Beckmann, Bradford M.

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,838,727
• Application Number: 16/220,508
• OSTI ID: 1771643
• Resource Relation: Patent File Date: 12/14/2018
• Country of Publication: United States
• Language: English