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Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

Journal Article · · IEEE Transactions on Power Electronics
 [1];  [2];  [2];  [3]
  1. University of Tennessee, Knoxville, TN (United States); University of Tennessee
  2. University of Tennessee, Knoxville, TN (United States)
  3. University of Tennessee, Knoxville, TN (United States); Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
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This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC mosfet -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

Research Organization:
University of Tennessee, Knoxville, TN (United States)
Sponsoring Organization:
USDOE Office of Energy Efficiency and Renewable Energy (EERE), Energy Efficiency Office. Advanced Materials & Manufacturing Office (AMMTO)
Grant/Contract Number:
EE0008410
OSTI ID:
1974605
Journal Information:
IEEE Transactions on Power Electronics, Journal Name: IEEE Transactions on Power Electronics Journal Issue: 2 Vol. 38; ISSN 0885-8993
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

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Figures / Tables (23)

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Related Subjects

42 ENGINEERING
Double pulse test (DPT)
medium voltage (MV)
parasitic capacitance
silicon carbide (SiC)
switching V-I timing alignment