Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Shang, Liuting; Naeemi, Azad; Pan, Chenyun

doi:10.1109/OJCS.2023.3247752

Title: Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Journal Article · Sun Jan 01 00:00:00 EST 2023 · IEEE Open Journal of the Computer Society

DOI:https://doi.org/10.1109/OJCS.2023.3247752· OSTI ID:1960068

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Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

In this article, we propose a generic design methodology to achieve area-efficient reconfigurable logic circuits by using exact synthesis based on Boolean satisfiability (SAT) solver. The proposed methodology better leverages the high representation ability of emerging reconfigurable logic gates (RLGs) to achieve reconfigurable circuits with fewer gates. In addition, we propose a fence-based acceleration method to provide >10× speed up for the synthesis without an observable loss of optimality. Furthermore, four sets of RLGs are developed based on a recently proposed valley-spin device as a case study to demonstrate the advantage of the proposed circuit. Simulations have been performed to analyze the impact of the fence searching algorithm and combination of operators. Based on disjoint-support decomposable (DSD) benchmarks, up to 38% and 73% reductions are observed in the area and energy-delay-area product (EDAP), respectively, compared to CMOS counterparts. Compared to the two existing synthesis methods, the proposed scheme provides 40% and 26.3% reduction in EDAP based on MCNC benchmark.

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Research Organization:: Univ. of Texas, Arlington, TX (United States)

Sponsoring Organization:: USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR); National Science Foundation (NSF)

Grant/Contract Number:: SC0022881; CCF-2219753

OSTI ID:: 1960068

Alternate ID(s):: OSTI ID: 1960900; OSTI ID: 1995724

Journal Information:: IEEE Open Journal of the Computer Society, Journal Name: IEEE Open Journal of the Computer Society Vol. 4; ISSN 2644-1268

Publisher:: Institute of Electrical and Electronics EngineersCopyright Statement

Country of Publication:: United States

Language:: English

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SAT solver
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valley-spin logic
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Title: Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

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