While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.
Bowman, Max Aksel, et al. "Hardware-Conscious Optimization of the Quantum Toffoli Gate." ACM Transactions on Quantum Computing, vol. 4, no. 4, Sep. 2023. https://doi.org/10.1145/3609229
Bowman, Max Aksel, Gokhale, Pranav, Larson, Jeffrey, Liu, Ji, & Suchara, Martin (2023). Hardware-Conscious Optimization of the Quantum Toffoli Gate. ACM Transactions on Quantum Computing, 4(4). https://doi.org/10.1145/3609229
@article{osti_1893328,
author = {Bowman, Max Aksel and Gokhale, Pranav and Larson, Jeffrey and Liu, Ji and Suchara, Martin},
title = {Hardware-Conscious Optimization of the Quantum Toffoli Gate},
annote = {While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.},
doi = {10.1145/3609229},
url = {https://www.osti.gov/biblio/1893328},
journal = {ACM Transactions on Quantum Computing},
issn = {ISSN 2643-6809},
number = {4},
volume = {4},
place = {United States},
publisher = {Association for Computing Machinery},
year = {2023},
month = {09}}
USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR); USDOE Office of Science (SC), Basic Energy Sciences (BES). Scientific User Facilities (SUF)
Grant/Contract Number:
SC0021526; AC02-06CH11357; AC05-00OR22725
OSTI ID:
1893328
Journal Information:
ACM Transactions on Quantum Computing, Journal Name: ACM Transactions on Quantum Computing Journal Issue: 4 Vol. 4; ISSN 2643-6809
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