The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.
@article{osti_1879965,
author = {Lotshaw, Phillip C. and Nguyen, Thien and Santana, Anthony and McCaskey, Alexander and Herrman, Rebekah and Ostrowski, James and Siopsis, George and Humble, Travis S.},
title = {Scaling quantum approximate optimization on near-term hardware},
annote = {The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.},
doi = {10.1038/s41598-022-14767-w},
url = {https://www.osti.gov/biblio/1879965},
journal = {Scientific Reports},
issn = {ISSN 2045-2322},
number = {1},
volume = {12},
place = {United States},
publisher = {Nature Publishing Group},
year = {2022},
month = {07}}
Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
Sponsoring Organization:
USDOE; Defense Advanced Research Projects Agency (DARPA); US Air Force Office of Scientific Research (AFOSR); US Army Research Office (ARO); National Science Foundation (NSF)
ASPLOS '19: Architectural Support for Programming Languages and Operating Systems, Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systemshttps://doi.org/10.1145/3297858.3304023