Skip to main content
OSTI.GOVU.S. Department of Energy Office of Scientific and Technical Information
U.S. Department of Energy
Office of Scientific and Technical Information
 

Bridging Python to Silicon: The SODA Toolchain

Journal Article · · IEEE Micro
 [1];  [1];  [2];  [1];  [3];  [1];  [1];  [1];  [1];  [2];  [2];  [1]
  1. Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
  2. Harvard Univ., Cambridge, MA (United States)
  3. Microsoft, Redmond, WA (United States)
+ Show Author Affiliations
Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.
Research Organization:
Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
Sponsoring Organization:
Defense Advanced Research Projects Agency (DARPA); USDOE
Grant/Contract Number:
AC05-76RL01830
OSTI ID:
1890940
Report Number(s):
PNNL-SA-169276
Journal Information:
IEEE Micro, Journal Name: IEEE Micro Journal Issue: 5 Vol. 42; ISSN 0272-1732
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

References (10)

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications conference December 2021
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration conference December 2021
Function Proxies for Improved Resource Sharing in High Level Synthesis
  • Minutoli, Marco; Castellana, Vito Giovanni; Tumeo, Antonino
  • 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines https://doi.org/10.1109/FCCM.2015.60
conference May 2015
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation conference April 2022
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis conference November 2021
High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers conference May 2021
A Hardware–Software Blueprint for Flexible Deep Learning Specialization journal September 2019
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics journal March 2022
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow journal January 2021
HeteroCL conference February 2019

Similar Records

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis
Conference · Wed Jul 07 00:00:00 EDT 2021 · OSTI ID:1827302
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators
Conference · Sun Nov 01 23:00:00 EST 2020 · OSTI ID:1752966
pnnl/soda-benchmarks
Software · Mon Jul 07 20:00:00 EDT 2025 · OSTI ID:code-157726

Related Subjects

97 MATHEMATICS AND COMPUTING
Codes
Compiler techniques
Field programmable gate arrays
Hardware
Hardware design languages
Hardware generation
High-level synthesis
Kernel
MLIR
Optimization
Silicon compiler
Synthesizers