SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Conference · Mon Nov 02 04:00:00 EST 2020

OSTI ID:1752966

Minutoli, Marco ^[1]; Castellana, Vito G. ^[1]; Tan, Cheng ^[1]; Manzano Franco, Joseph B. ^[1]; Amatya, Vinay C. ^[1]; Tumeo, Antonino ^[1]; Brooks, David ^[2]; Wei, Gu-Yeon ^[2]

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1. BATTELLE (PACIFIC NW LAB)
2. Harvard University

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

• Research Organization: Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1752966
• Report Number(s): PNNL-SA-155356
• Country of Publication: United States
• Language: English