U.S. Department of Energy Office of Scientific and Technical Information
A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies
This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200–300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable—using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods—this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.
Hazra, Sougata, et al. "A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies." Scientific Reports, vol. 12, no. 1, Jul. 2022. https://doi.org/10.1038/s41598-022-16281-5
Hazra, Sougata, Zhang, Chi, Wu, Qianying, et al., "A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies," Scientific Reports 12, no. 1 (2022), https://doi.org/10.1038/s41598-022-16281-5
@article{osti_1876476,
author = {Hazra, Sougata and Zhang, Chi and Wu, Qianying and Asheghi, Mehdi and Goodson, Kenneth and Dede, Ercan M. and Palko, James and Narumanchi, Sreekant},
title = {A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies},
annote = {Abstract This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200–300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable—using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods—this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.},
doi = {10.1038/s41598-022-16281-5},
url = {https://www.osti.gov/biblio/1876476},
journal = {Scientific Reports},
issn = {ISSN 2045-2322},
number = {1},
volume = {12},
place = {United Kingdom},
publisher = {Nature Publishing Group},
year = {2022},
month = {07}}
ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystemshttps://doi.org/10.1115/IPACK2020-2533
ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystemshttps://doi.org/10.1115/IPACK2020-2640