An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

Xiao, Tianyao Patrick; Feinberg, Benjamin; Bennett, Christopher H.; Agrawal, Vineet; Saxena, Prashant; Prabhakar, Venkatraman; Ramkumar, Krishnaswamy; Medu, Harsha; Raghavan, Vijay; Chettuvetty, Ramesh; Agarwal, Sapan; Marinella, Matthew J.

doi:10.1109/tcsi.2021.3134313

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

Journal Article · Tue Jan 04 00:00:00 EST 2022 · IEEE Transactions on Circuits and Systems I: Regular Papers

DOI:https://doi.org/10.1109/tcsi.2021.3134313· OSTI ID:1842837

^[1]; ^[1]; ^[1]; Agrawal, Vineet ^[2]; Saxena, Prashant ^[2]; Prabhakar, Venkatraman ^[2]; Ramkumar, Krishnaswamy ^[2]; Medu, Harsha ^[2]; Raghavan, Vijay ^[2]; Chettuvetty, Ramesh ^[2]; ^[1]; ^[3]

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Infineon Technologies LLC, San Jose, CA (United States)
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Arizona State Univ., Tempe, AZ (United States)

In this work, we demonstrate SONOS (silicon-oxide-nitrideoxide- silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a >10× gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

View Accepted Manuscript (DOE)

Research Organization:: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

Sponsoring Organization:: Defense Threat Reduction Agency (DTRA); USDOE Laboratory Directed Research and Development (LDRD) Program; USDOE National Nuclear Security Administration (NNSA)

Grant/Contract Number:: NA0003525

OSTI ID:: 1842837

Report Number(s):: SAND--2022-0047J; 703075

Journal Information:: IEEE Transactions on Circuits and Systems I: Regular Papers, Journal Name: IEEE Transactions on Circuits and Systems I: Regular Papers Journal Issue: 4 Vol. 69; ISSN 1549-8328

Publisher:: IEEECopyright Statement

Country of Publication:: United States

Language:: English

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97 MATHEMATICS AND COMPUTING
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An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

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