Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans

Patent · Tue Jul 07 00:00:00 EDT 2020

OSTI ID:1735010

Hamlet, Jason

Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.

• Research Organization: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• DOE Contract Number: NA0003525
• Assignee: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
• Patent Number(s): 10,706,181
• Application Number: 15/846,571
• OSTI ID: 1735010
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING