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Title: A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade

Journal Article · · Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
 [1];  [1];  [1];  [2];  [1];  [1]
  1. Univ. of Michigan, Ann Arbor, MI (United States)
  2. Academia Sinica, Taipei (Taiwan)
+ Show Author Affiliations

We present a multi-layer single-event upset mitigation strategy implemented in a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a trigger data router for the ATLAS muon spectrometer upgrade. The mitigation strategy employs three layers of protection to improve overall FPGA design robustness: use of triple-modular redundancy for FPGA fabric logic and embedded soft-error mitigation in the first layer; further enhancement with multi-boot FPGA reconfiguration across multiple copies of configuration memory in the second layer; and FPGA power cycling and configuration memory re-initialization in the third layer. Here, the effectiveness of this scheme has been evaluated at two different neutron facilities, LANSCE and NCSR ‘‘Demokritos’’, with 800 MeV and 25 MeV beam energies, respectively. Testing was performed with a similar configuration to that planned for final operation. We discuss the testing strategy and summarize the test results to estimate the expected data loss over 10 years of operation in the ATLAS experiment.

Research Organization:
Univ. of Michigan, Ann Arbor, MI (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP)
Grant/Contract Number:
SC0007859; SC0007857; AC02-98CH10886
OSTI ID:
1643338
Alternate ID(s):
OSTI ID: 1523546
Journal Information:
Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 939, Issue C; ISSN 0168-9002
Publisher:
ElsevierCopyright Statement
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 6 works
Citation information provided by
Web of Science

References (13)

FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics journal October 2015
Fixed-Latency Gigabit Serial Links in a Xilinx FPGA for the Upgrade of the Muon Spectrometer at the ATLAS Experiment journal January 2018
High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond journal March 2015
SRAM based re-programmable FPGA for space applications journal January 1999
FPGAs operating in a radiation environment: lessons learned from FPGAs in space journal February 2013
A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs journal October 2009
A Hybrid Approach to FPGA Configuration Scrubbing journal January 2017
An Analysis of High-Current Events Observed on Xilinx 7-Series and Ultrascale Field-Programmable Gate Arrays conference January 2016
Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation conference July 2014
Evaluating Xilinx 7 Series GTX Transceivers for Use in High Energy Physics Experiments Through Proton Irradiation journal December 2015
ATLAS Muon Drift Tube Electronics journal September 2008
The Use of Triple-Modular Redundancy to Improve Computer Reliability journal April 1962
SEE Measurements and Simulations Using Mono-Energetic GeV-Energy Hadron Beams journal December 2013

Cited By (1)

Radiation tolerance of online trigger system for COMET Phase-I text January 2020

Figures / Tables (10)

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TABLE III(p. 5)table TABLE III
Fig. 7(p. 6)figure Fig. 7
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TABLE V(p. 7)table TABLE V

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Related Subjects

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
FPGA
Radiation effect
Single-event upsets (SEUs)
Radiation hardening
Muon spectrometer
ATLAS