Optimizing Dynamic Timing Analysis with Reinforcement Learning
- Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
There are multiple factors involved in successfully manufacturing ASICIVLSI chips, and ensuring operational specifications are maintained throughout the design and manufacturing process is often challenging. Dynamic timing analysis (DTA) is the principal method used to validate that a manufactured chip complies to its design specifications. In DTA functionality of both synchronous and asynchronous designs are verified by applying input signals and checking for correct output signals. In complex designs where the number of input signal permutations is extremely large, the computing resources required to properly verify the functionality of a chip is prohibitive. In this paper, a strategy using reinforcement learning (RL) for reducing DTA time and resources in such cases is discussed. RL assisted DTA holds much promise in ensuring that VLSI chip design and functionality are fully and optimally verified.
- Research Organization:
- Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA); ALD
- DOE Contract Number:
- AC04-94AL85000; NA0003525
- OSTI ID:
- 1573933
- Report Number(s):
- SAND--2019-13625R; 681237
- Country of Publication:
- United States
- Language:
- English