skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Delayed boost of driver output signals

Patent ·
OSTI ID:1568252
;

According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Hewlett Packard Enterprise Development LP (Houston, TX)
Patent Number(s):
10,270,444
Application Number:
15/945,471
OSTI ID:
1568252
Resource Relation:
Patent File Date: 04/04/2018
Country of Publication:
United States
Language:
English

References (6)

Qualified universal clock buffer circuit for generating high gain, low skew local clock signals patent June 1998
High-performance, low-skew clocking scheme for single-phase, high-frequency global VLSI processor patent March 1998
Input buffer having dual paths patent October 2002
Increasing drive strength and reducing propagation delays through the use of feedback patent June 2005
Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges patent August 2005
Tri-state I/O port patent January 2011

Similar Records

Related Subjects

42 ENGINEERING
97 MATHEMATICS AND COMPUTING