MAC: Memory Access Coalescer for 3D-Stacked Memory

Conference · Tue Sep 03 04:00:00 EDT 2019

DOI:https://doi.org/10.1145/3337821.3337867· OSTI ID:1560132

Wang, Xi ^[1]; Tumeo, Antonino ^[2]; Leidel, John D. ^[3]; Li, Jie ^[1]; Chen, Yong ^[1]

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1. Texas Tech University
2. BATTELLE (PACIFIC NW LAB)
3. Tactical Computing Labs

Emerging data-intensive applications, such as graph analytics and data mining, exhibit irregular memory access patterns. Research has shown that with these memory-bound applications, traditional cache-based processor architectures, which exploit locality and regular patterns to mitigate the memory-wall issue, are inefficient. Meantime, novel 3D-stacked memory devices, such as Hybrid Mem- ory Cube (HMC) and High Bandwidth Memory (HBM), promise significant increases in bandwidth that appear extremely appealing for memory-bound applications. However, conventional memory interfaces designed for cache-based architectures and JEDEC DDR devices fit poorly with the 3D-stacked memory, which leads to significant under-utilization of the promised high bandwidth. As a response to these issues, in this paper we propose MAC (Memory Access Coalescer), a coalescing unit for the 3D-stacked memory. We discuss the design and implementation of MAC, in the context of a custom designed cache-less architecture targeted at data-intensive, irregular applications. Through a custom simulation infrastructure based on the RISC-V toolchain, we show that MAC achieves a coalescing efficiency of 52.85% on average. It improves the performance of the memory system by 60.73% on average for a large set of irregular workloads.

• Research Organization: Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1560132
• Report Number(s): PNNL-SA-144149
• Country of Publication: United States
• Language: English