Via configuration for wafer-to-wafer interconnection

Patent · 05 March 2019

OSTI ID:1525011

Jones, Adam

A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.

• Research Organization: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• DOE Contract Number: NA0003525
• Assignee: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
• Patent Number(s): 10,224,312
• Application Number: 15/603,100
• OSTI ID: 1525011
• Country of Publication: United States
• Language: English