Low-inductance direct current power bus

Neely, Jason C.; Stewart, Joshua; Delhotal, Jarod James; Flicker, Jack David; Brennecka, Geoff L.

Title: Low-inductance direct current power bus

Patent · Tue Sep 25 00:00:00 EDT 2018

OSTI ID:1482178

Neely, Jason C.; Stewart, Joshua; Delhotal, Jarod James; Flicker, Jack David; Brennecka, Geoff L.

A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.

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Research Organization:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC04-94AL85000

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Number(s):: 10,084,310

Application Number:: 15/426,844

OSTI ID:: 1482178

Resource Relation:: Patent File Date: 2017 Feb 07

Country of Publication:: United States

Language:: English

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