Low-inductance direct current power bus

Neely, Jason C.; Stewart, Joshua; Delhotal, Jarod James; Flicker, Jack David; Brennecka, Geoff L.

Low-inductance direct current power bus

Patent · Tue Sep 25 04:00:00 EDT 2018

OSTI ID:1482178

Neely, Jason C.; Stewart, Joshua; Delhotal, Jarod James; Flicker, Jack David; Brennecka, Geoff L.

A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.

Research Organization:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC04-94AL85000

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Number(s):: 10,084,310

Application Number:: 15/426,844

OSTI ID:: 1482178

Country of Publication:: United States

Language:: English

References (7)

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Miniature high voltage, high temperature component package development Rashkin, L. J.; Brocato, R. W.; Delhotal, J. J. 2016 IEEE International Power Modulator and High Voltage Conference (IPMHVC) https://doi.org/10.1109/IPMHVC.2016.8012810	conference	July 2016
Modeling of low inductive busbar connections Schanen, J. L.; Clavel, E.; Roudet, J. IEEE Industry Applications Magazine, Vol. 2, Issue 5, p. 39-43 https://doi.org/10.1109/2943.532153	journal	January 1996
Status quo and future prospects for metallized polypropylene energy storage capacitors Rabuffi, M.; Picci, G. IEEE Transactions on Plasma Science, Vol. 30, Issue 5 https://doi.org/10.1109/TPS.2002.805318	journal	October 2002
Modeling of busbars in high power neutral point clamped three-level inverters Yi, Rong; Zhao, Zhengming; Zhong, Yulin Tsinghua Science and Technology, Vol. 13, Issue 1, p. 91-97 https://doi.org/10.1016/S1007-0214(08)70015-4	journal	February 2008
Modeling of parasitic inductive effects in power modules Falck, E.; Stoisiek, M.; Wachutka, G. Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's https://doi.org/10.1109/ISPSD.1997.601452	conference	January 1997
Module-level paralleling of vertical GaN PiN diodes Flicker, Jack; Brocato, Robert; Delhotal, Jarod 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA) https://doi.org/10.1109/WiPDA.2016.7799925	conference	November 2016

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